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bluenrg - ms upgradable bluetooth ? low energy network processor datasheet - production data features ? bluetooth specification v4.1 compliant master and slave single - mode bluetooth low energy network processor ? embedded bluetooth low energy protocol stack: gap, gatt, sm, l2cap, ll, rf - phy ? bluetooth low energy profiles provided separately ? operating supply voltage: from 1.7 to 3.6 v ? 8.2 ma maximum tx current (@0 dbm, 3.0 v) ? down to 1.7 a current consumption with active ble stack ? integrated linear regulator and dc - dc step - down converte r ? up to +8 dbm available output power (at antenna connector) ? excellent rf link budget (up to 96 db) ? accurate rssi to allow power control ? proprietary application controller interface (aci), spi based, allows interfacing with an external host application microcontroller ? full link controller and host security ? high performance, ultra - low power cortex - m0 32 - bit based architecture core ? upgradable ble stack (stored in embedded flash memory, via spi) ? aes security co - processor ? low power modes ? 16 or 32 mhz crystal oscillator ? 12 mhz ring oscillator ? 32 khz crystal oscillator ? 32 khz ring oscillator ? battery voltage monitor ? compliant with the following radio frequency regulations: etsi en 300 328, en 300 440, fcc cfr47 part 15, arib std - t66 ? available in qfn32 (5 x 5 mm) and wlcsp34 (2.66 x 2.56 mm) packages ? operating temperature range: - 40 c to 85 c applications ? watches ? fitness, wellness and sports ? consumer medical ? security/proximity ? remote control ? home and industrial automation ? assisted living ? mobile phone peripherals ? pc peripherals table 1: device summary order code package packing bluenrg - ms qtr qfn32 (5 x 5 mm) tape and reel bluenrg - mscsp wlcsp34 (2.66 x 2.56 mm) tape and reel february 2016 docid027103 rev 6 1 / 42 www.st.com
list of tables bluenrg - ms contents 1 description ....................................................................................... 5 2 general description ......................................................................... 6 3 pin description ................................................................................ 8 4 application circuits ....................................................................... 11 5 block diagram and descriptions .................................................. 15 5.1 core, memory and peripherals ........................................................ 15 5.2 power management ........................................................................ 16 5.3 clock management ......................................................................... 17 5.4 bluetooth low energy radio .............................................................. 17 6 operating modes ........................................................................... 19 7 application controller interface .................................................... 22 8 absolute maximum ratings and thermal data ............................. 23 9 general characteristics ................................................................. 24 10 electrical specification .................................................................. 25 10.1 electrical characteristics .................................................................. 25 10.2 rf general characteristics .............................................................. 28 10.3 rf transmitter characteristics .......................................................... 28 10.4 rf receiver characteristics .............................................................. 29 10.5 high speed crystal oscillator (hsxosc) characteristics ................. 30 10.5.1 high speed crystal oscillator (hsxosc) .......................................... 31 10.6 low speed crystal oscillator (lsxosc) characteristics ................... 32 10.7 high speed ring oscillator (hsrosc) character istics ..................... 32 10.8 low speed ring oscillator (lsrosc) characteristics ....................... 32 10.9 n - fractional frequency synthesizer characteristics .......................... 32 10.10 auxiliary blocks characteristics ........................................................ 33 10.11 spi characteristics .......................................................................... 33 11 package information ..................................................................... 35 11.1 qfn32 package information ........................................................... 36 11.2 wlcsp34 package information ...................................................... 38 12 pcb assembly guidelines ............................................................. 40 13 revision history ............................................................................ 41 2 / 42 docid027103 rev 6
bluenrg - ms list of tables list of tables table 1: device summary ........................................................................................................................... 1 table 2: pinout description ......................................................................................................................... 9 table 3: external component list .............................................................................................................. 13 table 4: spi interface ............................................................................................................................... 15 table 5: bluenrg - ms operating modes .................................................................................................. 20 table 6: bluenrg - ms transition times ..................................................................................................... 21 table 7: absolute maximum ratings ......................................................................................................... 23 table 8: thermal data ............................................................................................................................... 23 table 9: recommended operating conditions .......................................................................................... 24 table 10: rf general characteristics ........................................................................................................ 28 table 11: rf transmitter characteristics .................................................................................................. 28 table 12: rf receiver characteristics ....................................................................................................... 29 table 13: high speed crystal oscillator characteristics ............................................................................. 30 table 14: low speed crystal oscillator characteristics .............................................................................. 32 table 15: high speed ring oscillator characteristics ................................................................................. 32 table 16: low speed ring oscillator characteristics .................................................................................. 32 table 17: n - fractional frequency synthesizer characteristics ................................................................... 33 table 18: auxiliary blocks characteristics ................................................................................................. 33 table 19: spi characteristics .................................................................................................................... 33 table 20: qfn32 (5 x 5 x 1 pitch 0.5 mm) mechanical data .................................................................... 37 table 21: wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data .................................................. 39 table 22: flip chip csp (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation ....... 40 table 23: document revision history ........................................................................................................ 41 docid027103 rev 6 3 / 42
list of figures blu enrg - ms list of figures figure 1: bluenrg - ms application block diagram ..................................................................................... 7 figure 2: bluenrg - ms pinout top view (qfn32) ....................................................................................... 8 figure 3: bluenrg - ms pinout top view (wlcsp34) ................................................................................. 8 figure 4: bluenrg - ms pinout bottom view (wlcsp34) ........................................................................... 9 figure 5: bluenrg - ms application circuit: active dc - dc converter qfn32 package ............................ 11 figure 6: bluenrg - ms application circuit: non active dc - dc converter qfn32 package ..................... 12 figure 7: bluenrg - ms application circuit: active dc - dc converter wlcsp package ........................... 12 figure 8: bluenr g - ms application circuit: non active dc - dc converter wlcsp package .................... 13 figure 9: block diagram ............................................................................................................................ 15 figure 10: power management strategy using ldo ................................................................................ 16 figure 11: power management strategy using step - down dc - dc converter .......................................... 17 figure 12: simplified state machine .......................................................................................................... 20 figure 13: simplified block diagram of the amplitude regulated oscillator ............................................... 31 figure 14: spi timings ............................................................................................................................... 34 figure 15: qfn32 (5 x 5 x 1 pitch 0.5 mm) package outline .................................................................... 36 figure 16: qfn32 (5 x 5 x 1 pitch 0.5 mm) package detail "a" ................................................................ 37 figure 17: wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline .................................................. 38 figure 18: flip chip csp (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation ...... 40 4 / 42 docid027103 rev 6
bluenrg - ms description 1 description the bluenrg - ms is a very low power bluetooth low energy (ble) single - mode network processor, compliant with bluetooth specification v4.1. the bluenrg - ms supports multiple roles simultaneously, and can act at the same time as bluetooth smart sensor and hub device. the bluetooth low energy stack runs on the embedded arm cortex - m0 core. th e stack is stored on the on - chip non - volatile flash memory and can be easily upgraded via spi. the device comes pre - programmed with a production - ready stack image (whose version could change at any time without notice). a different or more up - to - date stack image can be downloaded from the st web site and programmed on the device through the st provided software tools. the bluenrg - ms allows applications to meet of the tight advisable peak current requirements imposed with the use of standard coin cell batter ies. the maximum peak current is only 10 ma at 1 dbm of output power. ultra low - power sleep modes and very short transition times between operating modes allow very low average current consumption, resulting in longer battery life. the bluenrg - ms offers th e option of interfacing with external microcontrollers using spi transport layer. docid027103 rev 6 5 / 42
general description bluenrg - ms 2 general description the bluenrg - ms is a single - mode bluetooth low energy master/slav e network processor, compliant with the bluetooth specification v4.1. it integrates a 2.4 ghz rf transceiver and a powerful cortex - m0 microcontroller, on which a complete power - optimized stack for bluetooth single mode protocol runs, providing: ? master, sla ve role support ? gap: central, peripheral, observer or broadcaster roles ? att/gatt: client and server ? sm: privacy, authentication and authorization ? l2cap ? link layer: aes - 128 encryption and decryption an on - chip non - volatile flash memory allows on - field bluet ooth low energy stack upgrade. in addition, according the bluetooth specification v4.1 the bluenrg - ms can support the following features through firmware updates: ? multiple roles simultaneously support ? support simultaneous advertising and scanning ? support being slave of up to two masters simultaneously ? privacy v1.1 ? low duty cycle directed advertising the device allows applications to meet of the tight advisable peak current requirements imposed with the use of standard coin cell batteries. if the high effic iency embedded dc - dc step - down converter is used, the maximum input current is only 15 ma at the highest output power (+8 dbm). even if the dc - dc converter is not used, the maximum input current is only 29 ma at the highest output power, still preserving b attery life. ultra low - power sleep modes and very short transition time between operating modes result in very low average current consumption during real operating conditions, providing very long battery life. two different external matching networks are suggested: standard mode (tx output power up to +5 dbm) and high power mode (tx output power up to +8 dbm). the external host application processor, where the application resides, is interfaced with the bluenrg - ms through an application controller interfac e protocol which is based on a standard spi interface. 6 / 42 docid027103 rev 6
bluenrg - ms general description figure 1 : bluenrg - ms application block diagram docid027103 rev 6 7 / 42
pin description bluenrg - ms 3 pin description the bluenrg - ms pinout is shown in figure 2, figure 3 and figure 4. in table 2 a short description of the pins is provided. figure 2 : bluenrg - ms pinout top view (qfn32) figure 3 : bluenrg - ms pinout top view (wlcsp34) top view (balls are underneath). 8 / 42 docid027103 rev 6
bluenrg - ms pin description figure 4 : bluenrg - ms pinout bottom view (wlcsp34) table 2: pinout description pins name i/o description qfn32 wlcsp 1 e2 spi_mosi i spi_mosi 2 e1 spi_clk i spi_clk 3 d2 spi_irq o spi_irq 4 d1 test1 i/o test pin 5 c1 vbat3 vdd 1.7 - 3.6 battery voltage input 6 c2 test2 i/o test pin connected to gnd 7 b1 test3 i/o test pin connected to gnd 8 b2 test4 i/o test pin connected to gnd 9 a1 test5 i/o test pin connected to gnd 10 b3 test6 i/o test pin connected to gnd 11 a2 test7 i/o test pin connected to gnd 12 a3 vdd1v8 o 1.8 v digital core 13 a4 test8 i/o test pin not connected 14 a5 test9 i/o test pin not connected 15 b4 test11 i/o test pin not connected (qfn32) test pin connected to gnd (wlcsp) 16 b5 test12 i/o test pin not connected (qfn32) test pin connected to gnd (wlcsp) 17 a6 fxtal1 i 16/32 mhz crystal 18 b6 fxtal0 i 16/32 mhz crystal 19 - vbat2 vdd 1.8 - 3.6 battery voltage input 20 c6 rf1 i/o antenna + matching circuit 21 d6 rf0 i/o antenna + matching circuit 22 e6 sxtal1 i 32 khz crystal 23 e5 sxtal0 i 32 khz crystal 24 d5 vbat1 vdd 1.7 - 3.6 battery voltage input 25 e4 resetn i reset 26 f6 smpsfilt1 o smps output docid027103 rev 6 9 / 42
pin description bluenrg - ms pins name i/o description qfn32 wlcsp 27 - no_smps i power management strategy selection 28 f5 smpsfilt2 i/o smps input/output 29 f3 vdd1v2 o 1.2 v digital core 30 e3 test10 i/o test pin connected to gnd 31 f2 spi_cs i spi_cs 32 f1 spi_miso o spi_miso - c3 gnd gnd ground - d3 gnd gnd ground - d4 gnd gnd ground - f4 smps - gnd gnd smps ground 10/ 42 docid027103 rev 6
bluenrg - ms application circuits 4 application circuits the schematics below are purely indicative. for more detailed schematics, please refer to the "reference design" and "layout guidelines" which are provided as separate documents. figure 5 : bluenrg - ms application circuit: active dc - dc converter qfn32 package docid027103 rev 6 11/ 42
application circuits bluenrg - ms figure 6 : bluenrg - ms application circuit: non active dc - dc converter qfn32 package figure 7 : bluenrg - ms application circuit: active dc - dc converter wlcsp package 12/ 42 docid027103 rev 6
bluenrg - ms application circuits figure 8 : bluenrg - ms application circuit: non active dc - dc converter wlcsp package table 3: external component list component description c1 decoupling capacitor c2 dc- dc converter output capacitor c3 dc- dc converter output capacitor c4 decoupling capacitor for 1.2 v digital regulator c5 decoupling capacitor for 1.2 v digital regulator c6 decoupling capacitor c7 32 khz crystal loading capacitor (1) c8 32 khz crystal loading capacitor (1) c9 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c10 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c11 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c12 decoupling capacitor c13 decoupling capacitor c14 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c15 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode docid027103 rev 6 13/ 42
application circuits bluenrg - ms component description c16 rf balun/matching network capacitor high performance rf balun/matching network capacitor standard mode c17 16/32 mhz crystal loading capacitor c18 16/32 mhz crystal loading capacitor c19 decoupling capacitor for 1.8 v digital regulator c20 decoupling capacitor for 1.8 v digital regulator c21 rf balun/matching network capacitor high performance, rf balun/matching network capacitor standard mode l1 dc- dc converter input inductor, isat > 100 ma, q > 25 l2 rf balun/matching network inductor high performance rf balun/matching network inductor st andard mode l3 rf balun/matching network inductor high performance rf balun/matching network inductor standard mode l4 rf balun/matching network inductor high performance rf balun/matching network inductor standard mode r1 pull - down resistor on the spi_ irq line (can be replaced by the internal pull - down of the application mcu) xtal1 32 khz crystal (optional) xtal2 16/32 mhz crystal notes: (1) values valid only for the crystal ndk nx3215sa - 32.768 khz - exs00a - mu00003. for other crystals refer to what specified in their datasheet. 14/ 42 docid027103 rev 6
bluenrg - ms block diagram and descriptions 5 block diagram and descriptions a block diagram of the device is shown in figure 9: "block diagram" . in the following subsections a short description of each module is given. figure 9 : block diagram 5.1 core, memory and peripherals the bluenrg - ms contains an arm cortex - m0 microcontroller core that supports ultra - low leakage state retention mode and almost instantaneously returning to fully active mode on critical events. the memory subsystem consists of 64 kb flash, and 12 k b ram, divided in two blocks of 6 kb (ram1 and ram2). flash is used for the m0 program. no ram or flash resources are available to the external microcontroller driving the bluenrg - ms. the application controller interface (aci) uses a standard spi slave int erface as transport layer, basing in five physical wires: ? 2 control wires (clock and slave select) ? 2 data wires with serial shift - out (mosi and miso) in full duplex ? 1 wire to indicate data availability from the slave table 4: spi interface name direction w idth description spi_cs in 1 spi slave select = spi enable. spi_clk in 1 spi clock (max 8 mhz). spi_mosi in 1 master output, slave input. spi_miso out 1 master input, slave output. docid027103 rev 6 15/ 42
block diagram and descriptions bluenrg - ms name direction w idth description spi_irq out 1 slave has data for master. all the spi pins have an internal pull - down except for the csn that has a pull - up. all the spi pins, except the csn, are in high impedance state during the low - power states. the irq pin needs a pull - down external resistor. the device embeds a battery level detector to monitor the supply voltage. the characteristics of the battery level detector are defined in table 19 . 5.2 power management the bluenrg - ms integrates both a low dropout voltage regulator (ldo) and a step - down dc- dc converter, and one of them can be used to power the internal bluenrg - ms circuitry. however even when the ldo is used, the stringent maximum current requirements, which are advisable when coin cell batteries are used, can be met and further improvements can be obtained with the dc - dc converter at the sole additional cost of an inductor and a capacitor. the internal ldos supplying both the 1.8 v digital blocks and 1.2 v digital blocks require de coupling capacitors for stable operation. when the vbat voltage is below 1.8 v, the ldo 1.8 v output follows the vbat value. figure 10 and figure 11 , show the simplified power management sch emes using ldo and dc- dc converter. figure 10 : power management strategy using ldo 16/ 42 docid027103 rev 6
bluenrg - ms block diagram and descriptions figure 11 : power management strategy using step - down dc - dc converter 5.3 clock management the bluenrg - ms integrates two low - speed frequency oscillators (lsosc) and two high speed (16 mhz or 32 mhz) frequency oscillators (hsosc). the low frequency clock is u sed in low power mode and can be supplied either by a 32.7 khz oscillator that uses an external crystal and guarantee up to 50 ppm frequency tolerance, or by a ring oscillator with maximum 500 ppm frequency tolerance, which does not require any external components. the primary high frequency clock is a 16 mhz or 32 mhz crystal oscillator. there is also a fast - starting 12 mhz ring oscillator that provides the clock while the crystal oscillator is starting up. frequency tolerance of high speed crystal oscil lator is 50 ppm. the usage of the 16 mhz (or 32 mhz) crystal is strictly necessary. 5.4 bluetooth low energy radio the bluenrg - ms integrates a rf transceiver co mpliant to the bluetooth specification and to the standard national regulations in the unlicensed 2.4 ghz ism band. the rf transceiver requires very few external discrete components. it provides 96 db link budgets with excellent link reliability, keeping t he maximum peak current below 15 ma. in transmit mode, the power amplifier (pa) drives the signal generated by the frequency synthesizer out to the antenna terminal through a very simple external network. the power delivered as well as the harmonic content depends on the external impedance seen by the pa. docid027103 rev 6 17/ 42
block diagram and descriptions bluenrg - ms the output power is programmable from - 18 dbm to +8 dbm, to allow a user - defined power control system and to guarantee optimum power consumption for each scenario. 18/ 42 docid027103 rev 6
bluenrg - ms operating modes 6 operating modes several operating modes are defined for the bluenrg - ms: ? reset mode ? sleep mode ? standby mode ? active mode ? radio mode ? receive radio mode ? transmit radio mode in reset mode, the bluenrg - ms is in ultra - low power consumption: all voltage regulators, clocks and the rf interface are not powered. the bluenrg - ms enters reset mode by asserting the external reset signal. as soon as it is de - asserted, the device follows the normal activation sequence to tr ansit to active mode. in sleep mode either the low speed crystal oscillator or the low speed ring oscillator are running, whereas the high speed oscillators are powered down as well as the rf interface. the state of the bluenrg - ms is retained and the conte nt of the ram is preserved. depending on the application, part of the ram (ram2 block) can be switched off during sleep to save more power (refer to stack mode 1, described in um1868). while in sleep mode, the bluenrg - ms waits until an internal timer expir es and then it goes into active mode. the transition from sleep mode to active mode can also be activated through the spi interface. standby mode and sleep mode are equivalent but the low speed frequency oscillators are powered down. in standby mode the bl uenrg - ms can be activated through the spi interface. in active mode the bluenrg - ms is fully operational: all interfaces, including spi and rf, are active as well as all internal power supplies together with the high speed frequency oscillator. the mcu core is also running. radio mode differs from active mode as also the rf transceiver is active and it is capable of either transmitting or receiving. figure 12 reports the simplified state machine: docid027103 rev 6 19/ 42
operating modes bluenrg - ms figure 12 : simplified state machine table 5: bluenrg - ms operating modes state digital ldo spi lsosc hsosc core rf synt. rx chain tx chain reset off register contents lost off off off off off off off standby on register contents retained on off off off off off off sleep on register contents retained on on off off off off off active on register contents retained on - on on off off off rx on register contents retained on - on on on on off tx on register contents retained on - on on on off on 20/ 42 docid027103 rev 6
bluenrg - ms operating modes table 6: bluenrg - ms transition times transition maximum time condition reset - active (1) 1.5 ms 32 khz not available 7 ms 32 khz ro 94 ms 32 khz xo standby - active (1) 0.42 ms 32 khz not available 6.2 ms 32 khz ro 93 ms 32 khz xo sleep - active (1) 0.42 ms active -rx 125 s channel change 61 s no channel change active -tx 131 s channel change 67 s no channel change rx - tx or tx -rx 150 s notes: (1) these measurements are taken using nx3225sa - 16.000 mhz - exs00a - cs05997. docid027103 rev 6 21/ 42
application controller interface bluenrg - ms 7 application controller interface the application controller interface (aci) is based on a standard spi module with speeds up to 8 m hz. the aci defines a protocol providing access to all the services offered by the layers of the embedded bluetooth stack. the aci commands are described in the bluenrg - ms aci command interface document (um1865). in addition, the aci provides a set of comm ands that allow to program bluenrg - ms firmware from an external device connected to spi. the complete description of updater commands and procedures is provided in a separate application note (an4491). 22/ 42 docid027103 rev 6
bluenrg - ms absolute maximum ratings and thermal data 8 absolute maximum ratings and thermal data absolute maximum ratings are those values above which damage to the device may occur. functional operation under these conditions is not implied. all voltages are referred to gnd. table 7: absolute maximum ratings pin parameter value unit 5, 19, 24, 26, 28 dc- dc converter supply voltage input and output - 0.3 to +3.9 v 12, 29 dc voltage on linear voltage regulator - 0.3 to +3.9 v 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 25, 27, 30, 31, 32 dc voltage on digital input/output pins - 0.3 to +3.9 v 13, 14, 15,16 dc voltage on analog pins - 0.3 to +3.9 v 17, 18, 22, 23 dc voltage on xtal pins - 0.3 to +1.4 v 20, 21 (1) dc voltage on rf p ins - 0.3 to +1.4 v t stg storage temperature range - 40 to +125 c v esd - hbm electrostatic discharge voltage 2.0 kv notes: (1) +8 dbm input power at antenna connector in standard mode, +11 dbm in high power mode, with given reference design. table 8: thermal data symbol parameter value unit r thj - amb thermal resistance junction - ambient 34 (qfn32) 50 (wlcsp36) c/w r thj - c thermal resistance junction - case 2.5 (qfn32) 25 (wlcsp36) c/w docid027103 rev 6 23/ 42
general characteristics bluenrg - ms 9 general characteristics table 9: recommended operating conditions symbol parameter min. typ. max. unit v bat operating battery supply voltage 1.7 3.6 v t a operating ambient temperature range -40 +85 c 24/ 42 docid027103 rev 6
bluenrg - ms electrical specification 10 electrical specification 10.1 electrical characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat = 3.0 v. all perf ormance data are referred to a 50 w antenna connector, via reference design, qfn32 package version. symbol parameter test conditions min. typ. max. unit power consumption when dc - dc converter active ibat supply current reset 5 na standby ram2 off 1.3 a ram2 on 2 sleep 32 khz xo on (ram2 off) 1.7 a 32 khz xo on (ram2 on) 2.4 32 khz ro on (ram2 off) 2.8 32 khz ro on (ram2 on) 3.5 active cpu, flash and ram off 2 ma cpu, flash and ram on 3.3 rx high power mode 7.7 ma standard mode 7.3 tx standard mode +5 dbm 11 ma 0 dbm 8.2 - 2 dbm 7.2 - 6 dbm 6.7 - 9 dbm 6.3 -12 dbm 6.1 -15 dbm 5.9 -18 dbm 5.8 tx high power +8 dbm 15.1 ma docid027103 rev 6 25/ 42
electrical specification bluenrg - ms symbol parameter test conditions min. typ. max. unit mode +4 dbm 10.9 +2 dbm 9 - 2 dbm 8.3 - 5 dbm 7.7 power consumption when dc - dc converter not active ibat supply current reset 5 na standby ram2 off 1.4 a ram2 on 2 sleep 32 khz xo on (ram2 off) 1.7 a 32 khz xo on (ram2 on) 2.4 32 khz ro on (ram2 off) 2.8 32 khz ro on (ram2 on) 3.5 active cpu, flash and ram off 2.3 ma rx high power mode 14.5 ma standard mode 14.3 tx standard mode +5 dbm 21 ma 0 dbm 15.4 - 2 dbm 13.3 - 6 dbm 12.2 - 9 dbm 11.5 - 12 dbm 11 - 15 dbm 10.6 - 18 dbm 10.4 tx high power mode +8 dbm 28.8 ma +4 dbm 20.5 +2 dbm 17.2 - 2 dbm 15.3 - 5 dbm 14 - 8 dbm 13 - 11 dbm 12.3 26/ 42 docid027103 rev 6
bluenrg - ms electrical specification symbol parameter test conditions min. typ. max. unit - 14 dbm 12 digital i/o cin port i/o capacitance 1.29 1.38 1.67 pf trise rise time 0.1*vdd to 0.9*vdd, cl=50pf 5 19 ns tfall fall time 0.9*vdd to 0.1*vdd, cl=50pf 6 22 ns t(rst)l hold time for reset 1.5 ms tc vbat range 3 3.3 3.6 v tc1 vbat range 2.25 2.5 2.75 v tc2 vbat range 1.7 1.8 1.98 v vil input low voltage vbat range: tc vbat range: tc1 vbat range: tc2 - 0.3 0.8 v - 0.3 0.7 - 0.3 0.63 vih input high voltage vbat range: tc 2 3.6 v vbat range: tc1 1.7 3.6 vbat range: tc2 1.17 3.6 vol output low voltage vbat range: tc 0.4 v vbat range: tc1 0.7 vbat range: tc2 0.45 voh output high voltage vbat range: tc 2.4 v vbat range: tc1 1.7 vbat range: tc2 1.35 iol low level output current @vol (max) vbat range: tc 3.4 5.6 7.9 ma vbat range: tc1 3.8 6.6 10.1 vbat range: tc2 1.6 3 5 ioh high level output current @voh (min) vbat range: tc 5.5 10.6 17.6 ma vbatrange: tc1 3.7 7.2 12 vbat range: tc2 1.4 3 5.6 docid027103 rev 6 27/ 42
electrical specification bluenrg - ms 10.2 rf general characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v. all performance data are referred to a 50 w antenna connector, via reference design, qfn32 package version. t able 10: rf general characteristics symbol parameter test conditions min. typ. max. unit freq frequency range 2400 2483.5 mhz f ch channel spacing 2 mhz rf ch rf channel center frequency 2402 2480 mhz 10.3 rf transmitter characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat = 3.0 v. all perf ormance data are referred to a 50 w antenna connector, via reference design, qfn32 package version. table 11: rf transmitter characteristics symbol parameter test conditions min. typ. max. unit mod modulation scheme gfsk bt bandwidth - bit period product 0.5 m index modulation index 0.45 0.5 0.55 dr air data rate 1 mbps st acc symbol time accuracy 50 ppm p max maximum output power at antenna connector high power +8 +10 dbm standard mode +5 +7 dbm p rfc minimum output power high power -15 db standard mode -18 p rfc rf power accuracy 2 db p bw1m 6 db bandwidth for modulated carrier (1 mbps) using resolution bandwidth of 100 khz 500 khz p rf1 1 st adjacent channel transmit power 2 mhz using resolution bandwidth of 100 khz and average detector -20 dbm p rf2 2 nd adjacent channel transmit power >3 mhz using resolution bandwidth of 100 khz and average detector -30 dbm p spur spurious emission harmonics included. using resolution bandwidth of 1 mhz and average detector -41 dbm cf dev center frequency deviation during the packet and including both initial frequency offset and drift 150 khz 28/ 42 docid027103 rev 6
bluenrg - ms electrical specification symbol parameter test conditions min. typ. max. unit freq drift frequency drift during the packet 50 khz ifreq drift initial carrier frequency drift 20 khz driftrate max maximum drift rate 400 hz/s z load optimum differential load standard mode @ 2440 mhz 25.9 + j44.4 ? high power mode @ 2440 mhz 25.4 + j20.8 10.4 rf receiver characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v. all perfo rmance data are referred to a 50 w antenna connector, via reference design, qfn32 package version. table 12: rf receiver characteristics symbol parameter test conditions min. typ. max. unit rx sens sensitivity ber <0.1% - -88 dbm p sat saturation standard mode high power mode ber <0.1% 8 11 dbm z in input differential impedance standard mode @ 2440 mhz high power mode @ 2440 mhz 31.4 - j26.6 28.8 - j18.5 rf selectivity with ble equal modulation on interfering signal c/i co - channel co - channel interference wanted signal = - 67 dbm, ber 0.1% - 9 dbc c/i 1 mhz adjacent (+1 mhz) interference wanted signal = - 67 dbm, ber 0.1% 2 dbc c/i 2 mhz adjacent (+2 mhz) interference wanted signal = - 67 dbm, ber 0.1% -34 dbc c/i 3 mhz adjacent (+3 mhz) interference wanted signal = - 67 dbm, ber 0.1% -40 dbc c/i 4 mhz adjacent (?4 mhz) interference wanted signal = - 67 dbm, ber 0.1% -34 dbc c/i 6 mhz adjacent (?6 mhz interference wanted signal = - 67 dbm ber 0.1% -45 dbc c/i 25 mhz adjacent (?25 mhz) interference wanted signal = - 67 dbm, ber 0.1% -64 dbc c/i image image frequency interference - 2mhz wanted signal = - 67 dbm, ber 0.1% -20 dbc docid027103 rev 6 29/ 42
electrical specification bluenrg - ms symbol parameter test conditions min. typ. max. unit c/i image1 mhz adjacent (1 mhz) interference to in - band image frequency - 1mhz - 3mhz wanted signal = - 67 dbm, ber 0.1% 5 - 25 dbc out of band blocking (interfering signal cw) c/i block interfering signal frequency 30 mhz ? 2000 mhz wanted signal = - 67 dbm, ber 0.1%, measurement resolution 10 mhz - -30 dbm c/i block interfering signal frequency 2003 mhz ? 2399 mhz wanted signal = - 67 dbm, ber 0.1%, measurement resolution 3 mhz -35 dbm c/i block interfering signal frequency 2484 mhz ? 2997 mhz wanted signal = - 67 dbm, ber 0.1%, measurement resolution 3 mhz - -35 dbm c/i block interfering signal frequency 3000 mhz ? 12.75 ghz wanted signal = - 67 dbm, ber 0.1%, measurement resolution 25 mhz -30 dbm intermodulation characteristics (cw signal at f 1 , ble interfering signal at f 2 ) p_im(3) input power of im interferes at 3 and 6 mhz distance from wanted signal wanted signal = - 64 dbm, ber 0.1% - -33 dbm p_im( -3) input power of im interferes at - 3 and - 6 mhz distance from wanted signal wanted signal = - 64 dbm, ber 0.1% -43 dbm p_im(4) input power of im interferes at 4 and 8 mhz distance from wanted signal wanted signal = - 64 dbm, ber 0.1% -33 dbm p_im(5) input power of im interferes at 5 and 10 mhz distance from wanted signal wanted signal = - 64 dbm, ber 0.1% -33 dbm 10.5 high speed crystal oscillator (hsxosc) characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat = 3.0 v. table 13: high speed crystal oscillator characteristics symbol parameter test conditions min. typ. max. unit f nom nominal frequency 16/32 mhz f tol frequency tolerance includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance. 50 ppm esr equivalent series resistance 100 p d drive level 100 w 30/ 42 docid027103 rev 6
bluenrg - ms electrical specification 10.5.1 high speed crystal oscillator (hsxosc) the bluenrg - ms includes a fully integrated, low power 16/32 mhz xtal oscillator with an embedded amplitude regulation loop. in order to achieve low power operation and good frequency stability of the xtal oscillator, certain considerations with respect to the quartz load capacitance c0 need to be taken into account. figure 13 shows a simplified block diagram of the amplitude regulated oscillator used on the bluenrg - ms. figure 13 : simplified block diagram of the amplitude regulated oscillator low power consumption and fast startup time is achieved by choosing a quartz crystal with a low load capacitance c0. to achieve good frequency stability, the following equation needs to be satisfied: ? 0 = ? 1 ? ? 2 ? 1 + ? 2 where c1?=c1+cpcb1+cpad, c2?= c2+cpcb2+cpad, where c1 and c2 are external (smd) components, cpcb1 and cpcb2 are pcb routing para sites and cpad is the equivalent small - signal pad - capacitance. the value of cpad is around 0.5 pf for each pad. the routing parasites should be minimized by placing quartz and c1/c2 capacitors close to the chip, not only for an easier matching of the load capacitance c0, but also to ensure robustness against noise injection. connect each capacitor of the xtal oscillator to ground by a separate via. docid027103 rev 6 31/ 42
electrical specification bluenrg - ms 10.6 low speed crystal oscillator (lsxosc) characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v. table 14: low speed crystal oscillator characteristics symbol parameter test conditions min. typ. max. unit f nom nominal frequency 32.768 khz f tol frequency tolerance includes initial accuracy, stability over temperature, aging and frequency pulling due to incorrect load capacitance. 50 ppm esr equivalent series resistance 90 k p d drive level 0.1 w these values are the correct ones for nx3215sa - 32.768 khz - exs00a - mu00003. 10.7 high speed ring oscillator (hsrosc) characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, qfn32 package version. table 15: high speed ring oscillator characteristics symbol parameter test conditions min. typ. max. unit f nom nominal f requency 12 16 mhz 10.8 low speed ring oscillator (lsrosc) characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, qfn32 package version. table 16: low speed ring oscillator characteristics symbol parameter test conditions min. typ. max. unit 32 khz ring oscillator (lsrosc) f nom nominal frequency 37.4 khz f tol frequency tolerance 500 ppm 10.9 n - fractional frequency synthesizer characteristics characteristics measured over recommended operating conditions unless otherwise s pecified. typical value are referred to t a = 25 c, v bat =3.0 v, f c = 2440 mhz. 32/ 42 docid027103 rev 6
bluenrg - ms electrical specification table 17: n - fractional frequency synthesizer characteristics symbol parameter test conditions min. typ. max. unit pn synth rf carrier phase noise at 1 mhz offset from carrier -113 dbc/hz at 3 mhz offset from carrier -119 dbc/hz lock time pll lock time 40 s to time pll turn on / hop time including calibration 150 s 10.10 auxiliary blocks characteristics characteristics measured over recommended operating conditions unless otherwise specified. typical value are referred to t a = 25 c, v bat =3.0 v, f c = 2440 mhz. qfn32 package version. table 18: auxiliary blocks characteristics symbol parameter test conditions min. typ. max. unit battery indicator and brown - out reset (bor) (1) v blt1 battery level thresholds 1 2.7 v v blt2 battery level thresholds 2 2.5 v v blt3 battery level thresholds 3 2.3 v v blt4 battery level thresholds 4 2.1 v a blt battery level thresholds accuracy 5 % v abor ascending brown - out threshold 1.79 v v dbor descending brown - out threshold 1.73 v notes: (1) bor is disabled by default and it can be enabled by software. 10.11 spi characteristics table 19: spi characteristics symbol parameter min typ max unit f clk 1/t (clk) spi clock frequency 8 mhz ducy (clk) spi clock duty cycle 50 % t s(cs) cs setup time 40 ns t lh(cs) cs low hold time 40 t hh(cs) cs high hold time 10t (clk) t s(si) mosi setup time 20 t h(si) mosi hold time 10 t v(so) miso valid time 40 docid027103 rev 6 33/ 42
electrical specification bluenrg - ms the values for the parameters given in this table are based on characterization, not tested in production. figure 14 : spi timings 34/ 42 docid027103 rev 6
bluenrg - ms package information 11 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? speci fications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. docid027103 rev 6 35/ 42
package information bluenrg - ms 11.1 qfn32 package information figure 15 : qfn32 (5 x 5 x 1 pitch 0.5 mm) package outline 36/ 42 docid027103 rev 6
bluenrg - ms package information table 20: qfn32 (5 x 5 x 1 pitch 0.5 mm) mechanical data dim. mm min. typ. max. a 0.80 0.85 1.00 a1 0 0.02 0.05 a3 0.20 ref b 0.25 0.25 0.30 d 5.00 bsc e 5.00 bsc d2 3.2 3.70 e2 3.2 3.70 e 0.5 bsc l 0.30 0.40 0.50 0 14 k 0.20 figure 16 : qfn32 (5 x 5 x 1 pitch 0.5 mm) package detail "a" docid027103 rev 6 37/ 42
package information bluenrg - ms 11.2 wlcsp34 package information figure 17 : wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline 1. the corner of terminal a1 must be identified on the top surface by using a laser marking dot. 38/ 42 docid027103 rev 6 wlcsp34_poa_8165249 see note 1
bluenrg - ms package information table 21: wlcsp34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data dim. mm. notes min. typ. max. a 0.50 a1 0.20 b 0.27 (1) d 2.50 2.56 2.58 (2) d1 2.00 e 2.60 2.66 2.68 (3) e1 2.00 e 0.40 f 0.28 g 0.33 ccc 0.05 notes: (1) the typical ball diameter before mounting is 0.25 mm. (2) d = f + d1 + f. (3) e = g + e1 + g. docid027103 rev 6 39/ 42
pcb assembly guidelines bluenrg - ms 12 pcb assembly guidelines for flip chip mounting on the pcb, stmicroelectronics recommends the use of a solder stencil aperture of 330 x 330 m maximum and a typical stencil thickness of 125 m. flip chips are fully compatible with the use of near eutectic 95.8% sn, 3.5% ag, 0.7% cu solder paste with no - clean flux. st's recommendations for flip chip board mounting are illustrated on the soldering reflow profile shown in figure 17. figure 18 : flip chip csp (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation table 22: flip chip csp (2.66 x 2.56 x 0.5 pitch 0.4 mm) package reflow profile recommendation profile value typ. max. temp. gradient in preheat (t = 70 ? 180 c) 0.9 c/s 3 c/s temp. gradient (t = 200 ? 225 c) 2 c/s 3 c/s peak temp. in reflow 240 - 245 c 260 c time above 220 c 60 s 90 s temp. gradient in cooling - 2 to - 3 c/s - 6 c/s time from 50 to 220 c 160 to 220 s dwell time in the soldering zone (with temperature higher than 220 c) has to be kept as short as possible to prevent component and substrate damage. peak temperature must not exceed 260 c. controlled atmosphere (n 2 or n 2 h 2 ) is recommended during the wh ole reflow, especially above 150 c. flip chips are able to withstand three times the previous recommended reflow profile to be compatible with a double reflow when smds are mounted on both sides of the pcb plus one additional repair. a maximum of three s oldering reflows are allowed for these lead - free packages (with repair step included). the use of a no - clean paste is highly recommended to avoid any cleaning operation. to prevent any bump cracks, ultrasonic cleaning methods are not recommended. 40/ 42 docid027103 rev 6
bluenrg - ms revision history 13 revision history table 23: document revision history date revision changes 24- nov -2014 1 initial release. 19- jun - 2015 2 document status promoted from ?preliminary data? to ?production data?. minor changes in the structure of the document to improve readability. updated: figure in cover page, section 2: general description, figure 5, figure 6, figure 7, figure 8, section 10: electrical specification. added: figure 15: qfn32 (5 x 5 x 1 pitch 0.5 mm) package detail "a". 01- oct - 2015 3 modified: figure 5, figure 6, figure 7 and figure 8 29- oct - 2015 4 updated: general description. added: spi characteristics. 16- nov -2015 5 updated title, features , section 1: "description" and section 2: "general description". 01- feb - 2016 6 updated section 8: "application controller interface" docid027103 rev 6 41/ 42
bluenrg - ms important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved 42/ 42 docid027103 rev 6

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